1. Field of the Invention
The invention relates to digital filters and more specifically to digital decimation filters of the type currently referred to as Sinc-type digital decimation filters.
Such filters are currently used for performing a decimation action of the oversampled signal output from an analog/digital converter of the Sigma/Delta type.
Such a filter represents an optimal solution for decimation of such a signal due to its intrinsic simplicity and its low-pass filtering effect of the quantization noise in the signal. The designation xe2x80x9cSincxe2x80x9d derives from its transfer function in the frequency domain which is a power of the order N (N being the order the filter) of the function sinc(f)=sin(f)/f.
2. Description of the Related Art
A general review of decimation within the contest of Sigma/Delta modulation can be found in xe2x80x9cDecimation for Sigma/Delta Modulationxe2x80x9d by James C. Candy, IEEE Trans. Commun., vol. COM-34, pp. 72-76, January 1986.
The general layout of decimation digital filter of the Sinc type provides for N integrators operating at the sampling frequency of the input signal fs being arranged in a cascade followed by N derivative units operating at the decimation frequency fd=fs/M. N is designated the order of the Sinc filter while M is the decimation factor.
In FIG. 1 a block diagram is shown of a Sinc digital filter of order N=3, where the integrator and derivative stages are designated I and D, respectively.
There, blocks labeled zxe2x88x921 (in practice registers) represent delays of one sample, while each summation block implements a modulus arithmetic function (that is in the case of overflow the result is the remainder of the true value.
The transfer function Hp of a digital Sinc filter of order N and decimation factor M at the frequency fs simply derived from the transfer functions HI of integrators I and the transfer functions HD of derivative units D.
HI(z)=zxe2x88x921/(1xe2x88x92zxe2x88x921)
HD(z)=1xe2x88x92zxe2x88x92M
HP(z)=HINxc2x7HDN=zxe2x88x92Nxc2x7[(1xe2x88x92zxe2x88x92M)/(1xe2x88x92zxe2x88x921)]N
Specifically, the maximum gain of the transfer function HP occurs for de values and is equal to MN.
Properly implementing the structure shown in FIG. 1 requires the word length of each stage to be adequately selected in order to avoid overflow phenomena which would have a disruptive effect on the signal. Consequently, if b denotes the word length at the filter input, the required bit number does not need to be greater than:
n=b+┌Nxc2x7log2(M)┐
Using n bit words in all the stages of the filter ensures that no overflow will take place and that, similarly, no quantization noise will be introduced in addition to the quantization noise in the input signal.
However, the fact has to be taken into account that the number of bits bu in the output words from the filter (i.e., the output word length) is specific to the general design and is usually less than n: bu=nxe2x88x92k. Therefore, the output word from the filter must be diminished of the k least significant bits. This can be done either by implementing all the filter stages with n bit words while subsequently diminishing the output word or (with the main aim of reducing the chip area requirements) by diminishing the signal word also at intermediate points within the filter. This is usually done with a variable criterion by adopting error-minimizing criteria in such a way to obtain bu bit word at the output of the filter.
A simple solution known in the art provides for the 2N integration and derivative stages of the Sinc filter to be implemented by resorting to n bit words by effecting truncation or rounding-off to the bu bits of the output word by simply discarding the k least significant bits from the filter output or, alternatively, by using them for rounding-off the output word. In such a way the filter does not introduce any intermediate truncation or rounding error, while a truncation error q less than 2xe2x88x92(nxe2x88x92k) or rounding error q less than 2xe2x88x92(nxe2x88x92k+1) is introduced at the filter output.
Articles such as xe2x80x9cAn Economical Class of Digital Filters for Decimation and Interpolationxe2x80x9d by Eugene B. Hogenauer, IEEE Trans. on Acoustics, Speech and Signal Processing, vol. ASSP-29, no. 2, pp. 155-162, April 1981 or xe2x80x9cMultirate Filter Designs Using Comb Filtersxe2x80x9d by Shuni Chu et al., IEEE Trans. Circuits and Sys., vol. CS-31, pp. 913-924, November 1984 disclose methods which rely on the q error being in any case present at the filter output. Essentially, the methods disclosed in the referenced articles distribute truncation to k bits within the filter over the 2N derivative and integrator stages by adopting the empirical criterion of avoiding generation of an additional error higher than the final q truncation error. A specific example of this is described in the captioned article by Hogenauer.
The purpose of such methods is primarily reducing the components and the chip area required for implementing the filter. Such a reduction is achieved by implementing certain stages with a word length which is less than n bits and, therefore, with smaller adder blocks and registers. These methods, however, do not properly take into account the characteristics of the input signal and specifically the fact that the bandwidth of such an oversampled signal is usually much smaller than fs/2.
Also, in U.S. Pat. No. 6,057,793 to Dupuis et al. a digital decimation filter and method are disclosed wherein the decimation filter includes a front-end portion which receives the digital data at a relatively high sample rate. The first stage of the front-end portion involves decimation and a latter stage or stages of that portion involves combination of interpolation and decimation. The cumulative effect is to reduce the sample rate of the incoming data stream to a value which can be more easily manipulated by the back-end portion of the digital decimation filter.
An embodiment of the present invention improves the solution for eliminating the k least significant bits in a Sinc decimation filter by achieving advantages both in terms of chip area and as regard performance.
Essentially, in the arrangement of one embodiment of the invention reduction of k least significant bits takes place by truncating all the k least significant bits at the input of the first derivative unit, that is downstream of the cascaded integrators and upstream of the cascaded derivative units. In that way, all the derivative stages operate with nxe2x88x92k bit words.
In addition to reducing chip area and implementation complexity, in the current case of a suitably oversampled signal such a solution also ensures reduction of the quantization noise in the useful bandwidth of the signal thus leading to an improvement of the signal-to-noise ratio.
Having regard to the exceptions made on the characteristics of the input signal to the filter, the solution can be regarded as an optimal one, in that it ensures a signal-to-noise performance improved over any other truncation or rounding-off solution of the k least significant bits.